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Revision 0.6
OMAP TM 4 PandaBoard System
Reference Manual
November 29, 2010
DOC-21010
The supervisor IC at U20 has the DC input power tied to its VDD pin through a voltage divider. When
the voltage at the VDD input of this IC exceeds 1.40V (i.e. DCIN_JACK > 5.64V), the reset output of the
supervisor is negated. This will enable the two FETs at T1A and T1B, which will illuminate the red
overvoltage indicator, and disable the load switch at U17, which removes input power to the onboard
circuitry. The load switch at U15 that provides 5V USB Host power is enabled and disabled manually by
writing GPIO_1 to a ‘1’, or a ‘0’, respectively. The load switch at U15 powers up disabled.
2.7.2
USB/Ethernet Power Circuitry
There is a fixed 3.3V LDO (U11) that provides power for the LAN9514 Ethernet/USB Hub device. This
device is a Texas Instruments TPS73633DBVR device which can provide up to 400mA of output current.
This device may be controlled via S/W by writing OMAP4430 GPIO_1. Writing this GPIO high will
enable this LDO, while writing it low will disable it (see Table 9 on page 41). This device is shown on
sheet 11 of the schematic.
2.8
Standard Volatile Memory
The OMAP4430 processor supports two LPDDR2 channels, accessible only via a POP memory device
soldered on the 216-ball, 12x12 mm footprint on top of the OMAP4430 processor. Each channel
supports up to two chip-selects, so up to four LPDDR2 memory dies are supported. The two stacked
memory packages are directly connected to the two LPDDR2 EMIF4D interfaces of the OMAP4430 die.
The base address for the LPDDR2 is 0x8000 0000.
An 8Gb/1GB POP LPDDR2 DRAM device (Elpida P/N EDB8064B1PB-8D-F) is provided on the
PandaBoard. The memory device has four dies, with each die being a separate 2Gb LPDDR2.
2.9
Debug UART Interface
A single RS-232 port is provided on the PandaBoard via 9-pin D-sub female connector at location P4. It
provides access to the UART3 interface of the OMAP4430. See Figure 5 for the implementation of the
RS232 port.
The TXS0104EZXUR device at U21 is a voltage translator that translates between the 1.8V logic levels
required by the OMAP4430 processor to the 3.3V logic levels required by the SN75C3232EDR. The
SN75C3232EDR @ U24 is an RS-232 transceiver that converts the 3.3V logic signals to/from the voltage
translator (TXS0104EZXUR) to the RS-232 signal levels required (-5V to +5V).
The UART port at P4 can be accessed by using Teraterm or other terminal emulation program. To use
this UART interface, the serial port settings should be applied as follows:
?
?
BAUD RATE: 115200
DATA: 8 bit
Page 26 of 82
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相关PDF资料
UEVM4460G-02-01-00
PANDABOARD ES
UHDM7218BPA
PLATE BARRIER 71.86X17.87" GRY
UHDM7218ECA
PLATE END 71.86X17.87" GREY
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PLATE END 71.86X17.87" GREY
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PLATE BARRIER 83.9X17.9X0.1" GRY
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